Field of the Invention
The invention concerns an integrated semiconductor memory with a plurality of memory cells which are disposed in at least two memory banks.
Integrated semiconductor memories contain a plurality of memory cells. As shown in U.S. Pat. No. 5,109,265 the memory cells are divided into four memory banks.
From the applied supply voltage, different further voltages or potentials are generated on the integrated semiconductor memory and applied to the memory cell array. For example, a substrate bias is applied to the substrate; a word line voltage is applied to the word lines of the memory banks; and bit lines are supplied with a bit line voltage. A substrate potential is lower than the external supply voltage applied to the semiconductor chip, the word line voltage is above the externally applied supply voltage, and the bit line potential lies within the externally applied supply voltage. The power loss of the respective voltage generators is not insignificant, especially in the case of the substrate bias and the word line voltage.
Increasing storage capacity is also accompanied by increases in the capacitative loads to be driven by the respective voltage sources, e.g. the capacitance of word lines, bit lines or substrate. This demands high drive capability of the corresponding voltage generators. Thus with increasing storage capacity the power loss of the voltage sources also increases and can no longer be ignored compared with other sources of power loss. This effect becomes noticeable from a storage capacity of approximately 1 Gbit.
In Published, Non-Prosecuted German Patent Application DE 195 13 667 A1 a semiconductor memory is described for which the voltage generator for the word line voltage is driven with higher drive capability during a refresh or CBR mode and with lower drive capability at other times. All the memory cells under consideration are addressed by the same address decoder.